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an168 the i 2 c serial bus: theory and practical consideration using philips low-voltage pcf84cxx and pcd33xx m c families author: carl fenger 1988 dec integrated circuits
philips semiconductors application note an168 the i 2 c serial bus: theory and practical consideration using philips low-voltage pcf84cxx and pcd33xx m c families 2 1988 dec rev. 1 1993 dec author: carl fenger introduction the i 2 c (inter-ic) bus has become a popular serial bus architecture which needs to be understood for proper implementation. on the hardware level, i 2 c is a collection of microcomputers with integrated i 2 c port (philips pcd33xx, pcf84cxxx, and many of their 80(c)51 family derivatives, plus m cs from several other manufacturers), and a peripheral set (lcd/led drivers, ram, rom, e 2 prom, clock/calendars, i/o, a/d, d/a, ir transcoders, frequency synthesizers, audio processors, telephony ics and various tuning ics for tv/radio). these devices all communicate serially over a two-wire bus, serial data (sda) and serial clock (scl). the i 2 c structure is optimized for hardwire simplicity. parallel address and data buses inherent in conventional systems are replaced by a serial protocol that transmits both address and bidirectional data over a 2-wire bus. this means that interconnecting wires are reduced to a minimum; only v dd , ground, and the two-wire bus are required to link the controller(s) with the peripherals or other controllers. this results in reduced ic size, reduced pin count, and simpler interconnections. an i 2 c system is therefore smaller, simpler , and cheaper to implement than its parallel counterpart. the data rate of the i 2 c bus (100k bits/sec, with 400k bit/sec devices in development) makes it suited for systems that do not require high speed. the i 2 c architecture is thus well-suited for use in applications such as handheld products (telephone handsets, cordless phones), television and other consumer electronics, appliances, medical instruments, general instrumentation panels, and any application involving human interface. t ypically an i 2 c system would be used in a control function where digitally controllable elements are adjusted and monitored by a human user via a central processor. the i 2 c bus is an innovative hardware interface which provides the software designer the flexibility to create a truly multi-master environment. built into the serial interface of the controllers are status registers which monitor all possible bus conditions: bus free/busy , bus contention, slave acknowledgement, and bus interference. thus an i 2 c system might include several controllers on the same bus each with the ability to asynchronously communicate with peripherals or each other . this provision also provides expandability for future add-on controllers. (the i 2 c system is also ideal for use in environments where the bus is subject to noise. distorted transmissions are immediately detected by the hardware and the information presented to the software.) a slave acknowledgement on every byte also facilitates data integrity . an i 2 c system can be as simple or sophisticated as the operating environment demands. whether in a single master or multi-master system, noisy or `safe', correct system operation can be insured under software control. controllers the philips family of i 2 c microcontrollers and microprocessors has grown to encompass mainly devices based on the intel 8048, 8051, and motorola 68000 cores. these devices have various degrees of i 2 c port implementaion which dictates to which degree the i 2 c protocol generation and data transmission/reception is executed in hardware vs software. indeed, any standard microcontroller is capable of implementing i 2 c on a normal open-drain port, in which case the protocol is 100% software generated (`bit banging'). the i 2 c port itself, even when fully hardware implemented, requires only a handful of instructions to control and monitor the i 2 c bus. hence, the i 2 c port can be considered a core-independent interface. t wo families of philips microcontrollers which include members fully implementing the i 2 c interface on-chip are the pcf84cxxx and pcd33xx families of 8-bit low-voltage microcontrollers. these micros are optimized for low-power, low-voltage (v dd min. = 1.8v) and are hence ideal for battery powered, cordless products. these families implement the 8048 instruction set, with a few instructions deleted and replaced by i 2 c-port table 1. pcf84cxxx family instructions not in the instruction set serial i/o register control conditional branch mova,sn dec@rr sel mb2 jntf addr mov sn,a djnz@rr,addr sel mb3 mov sn,#data en si dis si table 2.pcf84cxxx instructions not in the 8400 family instruction set data moves flags branch control movxa,@r clrf0 *jni addr entoclk movxa,@r,a cplf0 jf0 addr movp3a,@a clrf1 jf1 addr movda,p cplf1 naldp,a orldp,a *replaced by jt0, jnt0 specific instructions. the i 2 c instructions involve moving data to and from the s0, s1, and s2 serial i/o control registers. the block diagram of the i 2 c interface is shown in figure 1. serial i/o interface a block diagram of the serial input/output (sio) of the pcf84cxxx family is shown in figure 1. the clock line of the serial bus (scl) has exclusive use of pin 3, while the serial data (sda) line shares pin 2 with parallel i/o signal p2.3 of port 2. consequently , only three i/o lines are available for port 2 when the i 2 c interface is enabled. communication between the cpu and i 2 c interface takes place via the internal bus of the microcomputer and the serial i/o interrupt request line (or via polling of status bits). four registers are used to store data and information controlling the operation of the interface: ? data shift register s0 ? address register s0' ? status register s1 ? clock control register s2 the i 2 c bus interface serial control registers s0, s1 all serial i 2 c transfers occur between the accumulator and register s0. the i 2 c hardware takes care of clocking out/in the data, and receiving/generating an acknowledge. in addition, the state of the i 2 c bus is controlled and monitored via the bus control register s1. a definition of the registers is as follows:
philips semiconductors application note an168 the i 2 c serial bus: theory and practical consideration using philips low-voltage pcf84cxx and pcd33xx m c families 1988 dec 3 dis si serial data i/o or i/o p23 of port 2 (pin 2) initialize (pin 17) reset es0 dig. filter data data control data data in out s0 bus busy logic arb. logic dig filter clock sclk (pin 3) bit 7 s2 clock multiplexer ack asc progr. counter clock sync logic & control bit 0 wr s2 s1 bit 7 bit 0 status register internal clock wr s1 rd s1 mst trx bb pin es0 al bc2 aas bc1 ado bco lrb internal microcomputer bus lrb aas ad0 pin sio interrupt logic clock control register serial clock pulse generator data shift register address comparator address backup latches als bit 7 bit 0 en si int req s0` wr s0` wr s0 rd s0 wr addr. latches 8400 interrupt logic bb al sl00947 figure 1. block diagram of the pcf84cxxx i 2 c interface data shift register s0 s0 is the data shift register used to perform the conversion between serial and parallel data format. all transmissions or receptions take place through register s0 msb first. all i 2 c bus receptions or transmissions involve moving data to/from the accumulator from/to s0. address register s0' in multi-master systems, this register is loaded with a controller's slave address. when activated, (als = 0), the hardware will recognize when it is being addressed by setting the aas (addressed as slave) flag. this provision allows a master to be treated as a slave by other masters on the bus. status register s1 s1 is the bus status register . to control the sio interface, information is written to the register . the lower 4 bits in s1 serve dual purposes; when written to, the control bits es0, bc2, bc1, bc0 are programmed (enable serial output and a 3-bit counter which indicates the current number of bits left in a serial transfer). when reading the lower four bits, we obtain the status information al, aas, ad0, lrb (arbitration lost, addressed as slave, address zero (the general call has been received), the last received bit (usually the acknowledge bit)). the upper 4 bits are the mst, trx, bb and pin control bits (master, transmitter, bus busy , and pending interrupt not). these bits define what role the controller has at any particular time. the values of the master and transmitter bits define the controller as either a master or slave (a master initiates a transfer and generates the serial clock; a slave does not), and as a transmitter or receiver . bus busy keeps track of whether the bus is free or not, and is set and reset by the `start' and `stop' conditions which will be defined. pending interrupt not is reset after the completion of a byte transfer + acknowledge, and can be polled to indicate when a serial transfer has been completed. an alternative to polling the pin bit is to enable the serial interrupt; upon completion of a byte transfer , an interrupt will vector program control to location 07h. clock control register (s2) the clock control register of the pcf84cxxx family defines the frequency of f sclk as the microcontroller clock frequency divided by an integer (t able 2). it also defines asc (asymmetrical clock) and ack (acknowledge). if asc=1, the generated sclk has a duty cycle of about 75%. the asymmetrical clock limites i 2 c bus transmission rate to below 55khz. divisors 39, 45 and 51 are not allowed if asc=1. however , an sclk duty cycle of about 50% results if asc=0. this permits i 2 c bus transmission rates of up to 100khz. all divisors of no tag are available. therefore, it is recommended to select asc=0. for the normal i 2 c bus protocol, ack must be set. after each byte transfer , an extra sclk pulse is generated during which the receiver may acknowledge reception. if ack
philips semiconductors application note an168 the i 2 c serial bus: theory and practical consideration using philips low-voltage pcf84cxx and pcd33xx m c families 1988 dec 4 3. f sclk as defined by clock control register s2 of the pcf84cxxx m c family cc4 to cc0 divisor of f xtal (df) f sclk (khz) at f xtal = 3.58mhz f sclk (khz) at f xtal = 10mhz f sclk (khz) at f xtal = 16mhz h`00' forbidden e e e h`01' 39 91.8 *256.4 *410.3 h`02' 45 79.5 *222.2 *355.6 h`03' 51 70.2 *196.1 *313.7 h`04' 63 56.8 *158.7 *254.0 h`05' 75 47.7 *133.3 *213.3 h`06' 87 41.1 *114.9 *183.9 h'07' 99 36.2 *101.0 *161.6 h`08' 123 29.1 81.3 *130.1 h`09' 147 24.4 68.0 *108.8 h`0a' 171 20.9 58.5 93.6 h`0b' 195 18.4 51.3 82.1 h`0c' 243 14.7 41.2 65.8 h`0d' 291 12.3 34.4 55.0 h`0e' 339 10.6 29.5 47.2 h'0f' 387 9.2 25.8 41.3 h`10' 483 7.4 20.7 33.1 h`11' 579 6.2 17.3 27.6 h`12' 675 5.3 14.8 23.7 h`13' 771 4.6 13.0 20.8 h`14' 963 3.7 10.4 16.6 h`15' 1155 3.1 8.7 13.9 h`16' 1347 2.7 7.4 11.9 h`17' 1539 2.3 6.5 10.4 h`18' 1923 1.9 5.2 8.3 h`19' 2307 1.6 4.3 6.9 h`1a' 2691 1.3 3.7 5.9 h`1b' 3075 1.2 3.3 5.2 h`1c' 3843 0.9 2.6 4.2 h`1d' 4611 0.8 2.2 3.5 h`1e' 5379 0.7 1.9 3.0 h`1f' 6147 0.6 1.6 2.6 *not permitted in non-fast i 2 c systems; maximum specified f sclk = 100khz. is zero, no acknowledge is generated. this mode is temporarily used when a master/receiver refuses the acknowledgement in order to signal an end of transmission to the slave transmitter (see the section on the bit counter bits bc0 to bc2 in the status register s1). the clock control register s2 is write-only. it can be written by mov s2,a and mov s2,#data. these speeds represent the frequency of the serial clock bursts and do not reflect the speed of the processor 's main clock (i.e., it controls the bus speed and has no ef fect on the cpu's execution speed). bus arbitration due to the wire-and configuration of the i 2 c bus, and the self-synchronizing clock circuitry of i 2 c masters, controllers with varying clock speeds can access the bus without clock contention. during arbitration, the resultant clock on the bus will have a low period equal to the longest of the low periods; the high period will equal the shortest of the high periods. similarly , when two masters attempt to drive the data line simultaneously , the data is `anded', the master generating a low while the other is driving a high will win
philips semiconductors application note an168 the i 2 c serial bus: theory and practical consideration using philips low-voltage pcf84cxx and pcd33xx m c families 1988 dec 5 arbitration. the resultant bus level will be low , and the loser will withdraw from the bus and set its `arbitration lost' flag (s1 bit 3). the losing master is now configured as a slave which could be addressed during this very same cycle. these provisions allow for a number of microcomputers to exist on the same bus. with properly written subroutines, software for any one of the controllers may regard other masters as transparent. pcf84cxxx scl sda pcf8574 pcf8570 i/o expandor addr = '40'h ram (256-byte) addr = 'a0'h a 0 a 1 a 2 a 0 a 1 a 2 v cc sl00948 figure 2. schematic for assembly examples i 2 c protocol and assembly language examples i 2 c data transfers follow a well-defined protocol. a transfer always takes place between a master and a slave. currently a microcomputer can be master or slave, while the `clips' peripherals are always slaves. in a `bus-free' condition, both scl and sda lines are kept logical high be external pull-up resistors. all bus transfers are bounded by a `start' and a `stop' condition. a `start' condition is defined as the sda line making a high-to-low transition while the scl line is high . at this point, the internal hardware on all slaves are activated and are prepared to clock-in the next 8 bits and interpret it as a 7-bit address and a r/w control bit (msb first). all slaves have an internal address (most have 23 programmable address bits) which is then compared with the received address. the slave that recodnized its address will respond by pulling the data line low during a ninth clock generated by the master (all i 2 c byte transfers require the master to generate 8 clock pulses plus a ninth acknowledge-related clock pulse). the slave-acknowledge will be registered by the master as a `0' appearing in the lrb (last received bit) position of the s1 serial i/o status register . if this bit is high after a transfer attempt, this indicates that a slave did not acknowledge and that the transfer should be repeated. after the desired slave has acknowledged its address, it is ready to either send or receive data in response to the master 's driving clock. all other slaves have withdrawn from the bus. in addition, for multi-master systems, the start condition has set the `bus busy' bit of the serial i/o register s1 on all masters on the bus. this gives a software indication to other master that the bus is in use and to wait until the bus is free before attempting an access. there are two types of i 2 c peripherals that now must be defined: there are those with only a chip address such as the i/o expandor , pcf8574, and those with a chip address plus an internal address such as the static ram, pcf8570. thus after sending a start condition, address, and r/w bit, we must take into account what type of slave is being addressed. in the case of a slave with only a chip address, we have already indicated its address and data direction (r/w ) and are therefore ready to send or receive data. this is performed by the master generating bursts of 9 clock pulses for each byte that is sent or received. the transaction for writing one byte to a slave with a chip address only is shown in figure 3. in this transfer , all bus activity is invoked by writing the appropriate control byte to the serial i/o control register s1, and by moving data to/from the serial bus buf fer register s0. coming from a known state (mov s1, #18h-slave, receiver, bus not busy) we first load the serial i/o buffer s0 with the desired slave's address (mov s0, #40h). t o transmit this preceded by a start condition, we must first examine the control register s1, which, after initialization, looks like this: mas- 0 0 0 1 1 0 0 0 ter trans bus busy pin es0 bc2 bc1 bc0 to transmit to a slave, the master, transmitter, bus busy, pin (pending interrupt not), and eso (enable serial output) must be set to a 1. this results in an `f8h' being written to s1. this word defines the controller as a master transmitter, invokes the transfer by setting the `bus busy' bit, clears the pending interrupt not (an active low flag indicating the completion of a compete byte transfer), and activates the serial output logic by setting the enable serial output (eso) bit. bit counter s12, s11, s10 bc2, bc1 and bc0 comprise a bit-counter which indicates to the logic how long the word is to be clocked out over the serial data line. by setting this to a 000h, we are telling it to produce 9 clocks (8 bits plus an acknowledge clock) for this transfer . the bit counter will then count of f each bit as it is transmitted. the bit counter possibilities are shown in no tag. thus, the bit counter keeps track of the number of clock pulses remaining in a serial transfer. additionally, there is a not-acknowledge mode (controlled through bit 6 of clock control register s2) which inhibits the acknowledge clock pulse, allowing the possibility of straight serial transfer. we may thus define the word size for a serial transfer (by pre-loading bc2, bc1, bc0 with the appropriate control number), with or without an acknowledge-related clock pulse being generated. this makes the controller able to transmit serial data to most any serial device regardless of its protocol (e.g., c-bus devices).
philips semiconductors application note an168 the i 2 c serial bus: theory and practical consideration using philips low-voltage pcf84cxx and pcd33xx m c families 1988 dec 6 mov s1, #18h mov s0, #40h mov s1, #0f8h call ackwt: mov a, #2ah mov s0,a call ackwt: mov s1, #0d8h sda scl start condition address '40h' data '2ah' stop condition acknowledge rd/wr :initialize s1-slave, receiver, bus not :busy, enable serial i/o :preload s0 with slave's address & :r/w bit :invoke start condition & slave address :(master, transmitter, bus busy, enable :serial i/o, bit counter = 000) :check for transmission complete, ack :received, no arbitration, etc. :get a data byte :transmit data byte :wait for transmission complete again :generate stop condition :(master, transmitter, bus not busy) sl00949 figure 3. table 4.binary numbers in bit-count locations bc2, bc1 and bc0 bc2 bc1 bc0 bits/byte without ack bits/byte with ack 0 0 1 1 2 0 1 0 2 3 0 1 1 3 4 1 0 0 4 5 1 0 1 5 6 1 1 0 6 7 1 1 1 7 8 0 0 0 8 9 checking for slave acknowledge after a `start' condition and address have been issued, the selected slave will have recognized and acknowledged its address by pulling the data line low during the ninth clock pulse. during this period, the software (which runs on the processor's main clock) will have been either waiting for the transfer to be completed by polling the pin bit in s1 which goes low on completion of a transfer/reception (whose length is defined by the pre-loaded bit-counter value), or by the hardware in serial interrupt mode. the serial interrupt (vectored to 07h) is enabled via the en si (enable serial interrupt) instruction. at the point when pin goes low (or the serial interrupt is received) the 9-bit transfer has been completed. the acknowledgement bit will now be in the lrb position of register s1, and may be checked in the routine `ackwt' (wait for acknowledge) as shown in figure 4. this routine must go one step further in multi-master systems; the possibility of an arbitration lost situation may occur if other masters are present on the bus. this condition may be detected by checking the `al ' bit (bit 3). if arbitration has been lost, provisions for re-attempting the transmission should be taken. if arbitration is lost, there is the possibility that the controller is being addressed as a slave. if this condition is to be recognized, we must test on the `aas' bit (bit 2). a `general call' address (00h) has also been defined as an `all-call' address for all slaves; bit 1, ad0, must be tested if this feature is to be recognized by a master . after a successful address transfer/acknowledge, the slave is ready to be sent its data. the instruction mov s0,a will now automatically send the contents of the accumulator out on the bus. after calling the ackwt routine once more, we are ready to terminate the transfer . the stop condition is created by the instruction `mov s1, #0d8h'. this re-sets the bus-busy bit, which tells the hardware to generate a stop the data line makes a low-to-high transition while the clock remains high. all bus-busy flags on other masters on the bus are reset by this signal.
philips semiconductors application note an168 the i 2 c serial bus: theory and practical consideration using philips low-voltage pcf84cxx and pcd33xx m c families 1988 dec 7 the transfer is now complete pcf8574 i/o expandor will transfer the serial data stream to its 8 output pins and latch them until further update. ackwt: mov a,s1 ;get bus status word ;from s1. jb4 ackwt ;poll the pin bit ;until it goes low ;indicating transfer ;completed jbo buserr ;jump to buserr ;routine if acknowledge ;not received. ret ;transfer complete, ;acknowledge received return. sl00950 figure 4. master reads one byte from slave a read operation is a similar process; the address, however , will be 41h, the lsb indicating to the i/o device that a read is to be performed. during the data portion of a read, the i/o port 8574 will transmit the contents of its latches in response to the clock generated by the master. the master/receiver in this case generates a low-level acknowledge on reception of each byte (a `positive' acknowledge). upon completion of a read, the master must generate a `negative' acknowledge during the ninth clock to indicate to the slaves that the read operation is finished. this is necessary because an arbitrary number of bytes may be read within the same transfer . a negative acknowledge consists of a high signal on the data line during the ninth clock of the last byte to be read. t o accomplish this, the master must leave the acknowledge mode just before the final byte, read the final byte (producing only 8 clock pulses), program the bit-counter with 001 (preparing for a one-bit negative acknowledge pulse), and simply move the contents of s0 to the accumulator . this final instruction accomplishes two things simultaneously: it transfers the final byte to the accumulator and produces one clock pulse on the scl line. the structure of the serial i/o register s0 is such that a read from it causes a double-buffered transfer from the i 2 c bus to s0, while the original contents of s0 are transferred to the accumulator . because the number of clocks produced on the bus is determined by the control number in the bit counter , by presetting it to 001, only one clock is generated. at this point in time the slave is still waiting for an acknowledge; the bus is high due to the pull-up, as single clock pulse in this condition is interpreted as a `negative' acknowledge. the slave has now been informed that reading is completed, a stop condition is now generated as before. the read process (one byte from a slave with only a chip address) is shown in figure 5. these examples apply to a slave with a chip address more than one byte can be written/read within the same transfer; however , this option is more applicable to i 2 c devices with sub-addresses such as the static rams or clock/calendar. in the case of these types of devices, a slightly dif ferent protocol is used. the ram, for example, requires a chip address and an internal memory location before it can deliver or accept a byte of information. during a write operation, this is done by simply writing the secondary address right after the chip address the peripheral is designed to interpret the second byte as an internal address. in the case of a read operation, the slave peripheral must send data back to the master after it has been addressed and sub-addressed. to accomplish this, first the start, address, and sub-address is transmitted. then we have repeated start condition to reverse the direction of the data transfer , followed by the chip address and rd, than a data string (w/acknowledges). this repeated start does not affect other peripherals they have been deactivated and will not reactivate until a stop condition is detected. i 2 c peripherals are equipped with auto-incrementing logic which will automatically transmit or receive data in consecutive (increasing) locations. for example, to read 3 consecutive bytes to pcf8571 ram locations 00, 01 and 02, we use the following format as shown in figure 7. this routine reads the contents of location 00, 01 and 02 of the pcf8570 256-byte ram and puts them in registers r0, r1, and r2. the auto-incrementing feature allows the programmer to indicate only a starting location, then read an arbitrary block of consecutive memory addresses. the w ait 1 loop is required to poll for the completion of the final byte because the ackwt routine will not recognize the negative acknowledge as a valid condition. bus error conditions: acknowledge not received in the above routines, should a slave fail to acknowledge, the condition is detected during the `ackwt' routine. the occurrence may indicate one of two conditions: the slave has failed to operate, or a bus disturbance has occurred. the software response to either event is dependent on the system application. in either case, the `buserr ' routine should reinitialize the bus by issuing a `stop' condition. provision may then be taken to repeat the transfer an arbitrary number of times. should the symptom persist, either an error condition will be entered, or a backup device can be activated. these sample routines represent single-master systems. a more detailed analysis of multi-master/noisy environment systems are treated in other application notes. for more complex systems, the 80c51 derivative microcontrollers with i 2 c interface are recommended. philips 80c51 micros implement a slightly modified i 2 c interface and conventions, but operate in a similar fashion to the micros described here. (see philips semiconductors an430, athe 83/87c51/752 in a multi-master i 2 c environmento.)
philips semiconductors application note an168 the i 2 c serial bus: theory and practical consideration using philips low-voltage pcf84cxx and pcd33xx m c families 1988 dec 8 `negative acknowledge' mov s1, #18h mov s0, #40h mov s1, #0f8h call ackwt: mov s2, #01h mov s0,a mov s1, #0d8h sda scl start condition address '40h' data stop condition acknowledge rd :initialize serial i/o control :register :preload serial register s0 :with slave address and rd :control bit :send address to bus along with :start condition :wait for acknowledge (as :before) :leave acknowledge mode :read data from slave to s0 :test for byte received by :testing s1 pin bit :wait until pin received :set bit counter to 1 and :become a receiver (a9 = :mst, rec, bus busy, bit counter = :0001) :move data to accumulator and :clock out a negative :acknowledge :generate stop condition mov s0,a mov s1, #0a9h jb4 wait mov a,s1 wait: sl00951 figure 5.
philips semiconductors application note an168 the i 2 c serial bus: theory and practical consideration using philips low-voltage pcf84cxx and pcd33xx m c families 1988 dec 9 pin & ack received ? initialize bus status load s0 with slave address and rd/wr bit start condition and transmit address return generate stop condition send/receive data byte yes no no yes pin & ack received ? generate stop condition communication with peripheral required sl00952 figure 6. flowchart for reading/writing one byte to an i 2 c peripheral; single-master, single-address slave mov s1, #18h :initialize bus-status register :master, transmitter, :bus-not-busy, enable sio, mov s0, #0a0h :load s0 with ram's chip :address mov s1, #0f8h :start cond. and transmit :address call ackwt :wait until address received mov a, #00h :set up for transmitting ram :location address mov s0,a :transmit first ram address call ackwt :wait mov s1, #18h :set up for a repeated start :condition mov a, #0a1h :get ram chip address & rd bit mov so, a :send out to bus mov s1, #0f8h :preceded by repeated start call ackwt :wait mov a,s0 :first data byte to s0 call ackwt :wait mov a,s0 :second data byte to s0 :and first data byte to acc. call ackwt :wait mov r0,a :save first byte in r0 mov a,s0 :third data byte to s0 :and second data byte to acc. call ackwt :wait mov r1,a :save second data byte :in r1 mov s2, #01h :leave ack. mode :bit counter=001 for neg ack. mov a,s0 :third data byte to acc :negative ack. generated mov r2,a :save third data byte in r2 mov a,s1 :get bus status jb4 wait1 :wait until transfer complete mov s1, #0d8h :stop condition mov s2, #41h :restore acknowledge mode wait1: sl00953 figure 7.
philips semiconductors application note an168 the i 2 c serial bus: theory and practical consideration using philips low-voltage pcf84cxx and pcd33xx m c families 1988 dec 10 assigned i 2 c bus addresses i 2 c address part number function a6 a5 a4 a3 a2 a1 a0 general call address 0 0 0 0 0 0 0 reserved addresses 0 0 0 0 x x x pcd3311/12 t one generator dtmf/modem/musical 0 1 0 0 1 0 a pcf8200 voice synthesizer (male or female) 0 0 1 0 0 0 0 pcf8566 96-segment lcd driver 1:11:4 mux 0 1 1 1 1 1 a pcf8568 lcd row driver for dot matrix displays 0 1 1 1 1 0 a pcf8569 column driver for dot matrix displays 0 1 1 1 1 0 a pcf8570/71 256 8, 128 8 static ram 1 0 1 0 a a a pcf8570c 256 8 static ram 1 0 1 1 a a a pcf8573 clock/calendar 1 1 0 1 0 a a pcf8574 i 2 c bus to 8-bit bus converter 0 1 0 0 a a a pcf8574a i 2 c bus to 8-bit bus converter 0 1 1 1 a a a pcf8576 160-segment lcd driver 1:11:4 mux 0 1 1 1 0 0 a pcf8577 64-segment lcd driver 1:11:2 mux 0 1 1 1 0 1 0 pcf8577a 64-segment lcd driver 1:11:2 mux 0 1 1 1 0 1 1 pcf8578 row/column lcd dot-matrix driver 0 1 1 1 1 0 a pcf8579 row/column lcd dot-matrix driver 0 1 1 1 1 0 a pcf8581 128-byte eeprom 1 0 1 0 a a a pcf8582 256 8 eeprom 1 0 1 0 a a a pcf8583 256 8 ram with clock/calendar 1 0 1 0 0 0 a pcf8591 4-channel, 8-bit a/d plus 8-bit d/a 1 0 0 1 a a a pcf8594 512-byte eeprom 1 0 1 0 a a a saa1064 4-digit led driver 0 1 1 1 0 a a saa1136 pcm-audio indent-word interface 0 0 1 1 1 1 0 saa1300 5-bit high current driver 0 1 0 0 0 a a saa5243/45 enhanced teletext circuit 0 0 1 0 0 0 1 saa7191 s-vhs digital multistandard decoder asquare pixelo 1 0 0 0 1 a 1 saa7192 digital color space converter 1 1 1 0 0 0 a saa7199 digital encoder 1 0 1 1 0 0 0 saa9020 field memory controller 0 0 1 0 1 a a saa9051 digital multi-standard tv decoder 1 0 0 0 1 0 1 saa9068 (pipco) picture-in-picture controller 0 0 1 0 0 1 a sab3035/36/37 (cit ac) cpu interface for tuning and control 1 1 0 0 0 a a saf1135 data line decoder 0 0 1 0 0 a a tda4670 picture signal improvement circuit 1 0 0 0 1 0 0 tda4680 video processor 1 0 0 0 1 0 0 tda8421 hi-fi stereo audio processor 1 0 0 0 0 0 a tda8425 audio processor w/loudspeaker channel 1 0 0 0 0 0 1 tda8440 switch for ctv receivers 1 0 0 1 a a a tda8442 interface for color decoders 1 0 0 0 1 0 0 tda8443 yuv/rgb interface circuit 1 1 0 1 a a a tda8444 octuple 6-bit dac 0 1 0 0 a a a tda8461 pal/ntsc color decoder 1 0 0 0 1 0 a tea6100 fm/if and tuning interface 1 1 0 0 0 0 1 tea6300/6310t sound fader control circuit 1 0 0 0 0 0 0 tsa5511/12/14 pll frequency synthesizer for tv 1 1 0 0 0 a a tsa6057 radio tuning pll frequency synthesizer 1 1 0 0 0 1 a umf1009 frequency synthesizer 1 1 0 0 0 a a reserved addresses 1 1 1 1 x x x x = don't care. a = can be connected high or low by the user .

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